1. Field of the Invention
This invention relates generally to semiconductor processing, and more particularly to thermal management structures for stacked semiconductor chips and to methods of assembling the same.
2. Description of the Related Art
Stacked semiconductor chip devices present a host of design and integration challenges for scientists and engineers. Common problems include providing adequate electrical interfaces between the stacked semiconductor chips themselves and between the individual chips and some type of circuit board, such as a motherboard or semiconductor chip package substrate, to which the semiconductor chips are mounted. Another critical design issue associated with stacked semiconductor chips is thermal management. Most electrical devices dissipate heat as a result of resistive losses, and semiconductor chips and the circuit boards that carry them are no exception. Still another technical challenge associated with stacked semiconductor chips is testing.
Thermal management of a semiconductor chip or chips in a stacked arrangement remains a technical challenge during required electrical testing of one or more of the semiconductor chips. A given semiconductor chip in a stacked arrangement, whether the first, an intermediary or the last in the particular stack, may dissipate heat to such an extent that active thermal management is necessary in order to either prevent the one or all of the semiconductor chips in the stack from entering thermal runaway or so that one or more of the semiconductor chips in the stack may be electrically tested at near or true operational power levels and frequencies.
Some conventional chip stack designs utilize electrically functional micro bumps to establish die-to-die electrical interfaces. These electrically functional micro bumps can transfer some heat from one die to the next. However, the footprints of such electrically functional micro bumps can be relatively small. These electrically functional micro bumps may only cover a small percentage of the surface of a given chip, and thus be inadequate as heat dissipation pathways.
The present invention is directed to overcoming or reducing the effects of one or more of the foregoing disadvantages.